View X9221A06_708852.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
X9221A
64 Taps, 2-Wire Serial Bus
Data Sheet August 30, 2006 FN8163.2
Dual Digitally Controlled Potentiometer (XDCPTM)
FEATURES * Two XDCPs in one package * 2-wire serial interface * Register oriented format, 8 registers total --Directly write wiper position --Read wiper position --Store as many as four positions per pot * Instruction format --Quick transfer of register contents to resistor array * Direct write cell --Endurance-100,000 writes per bit per register * Resistor array values --2k, 10k, 50k * Resolution: 64 taps each pot * 20 Ld plastic DIP and 20 Ld SOIC packages * Pb-free plus anneal available (RoHS compliant) BLOCK DIAGRAM
DESCRIPTION The X9221A integrates two digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated microcircuit. The digitally controlled potentiometer is implemented using 63 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the 2-wire bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and 2 nonvolatile Data Registers (DR0:DR1) that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array through the switches. Power up recalls the contents of DR0 to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.
Pot 0 VCC VSS R0 R1 Wiper Counter Register (WCR) VH0/RH0
R2 R3 SCL SDA A0 A1 A2 A3
VL0/RL0 VW0/RW0
Interface and Control Circuitry Data
8
R0 R1
VH1/RH1 Wiper Counter Register (WCR) Register Array Pot 1
R2 R3
VL1/RL1 VW1/RW1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X9221A Ordering Information
PART NUMBER X9221AYS X9221AYSZ (Note) X9221AYSI* X9221AYSIZ* (Note) X9221AWS* X9221AWSZ* (Note) X9221AWSI* X9221AWSIZ* (Note) X9221AUP X9221AUPZ (Note) X9221AUPI X9221AUPIZ (Note) X9221AUSI* X9221AUSIZ* (Note) PART MARKING X9221AYS X9221AYS Z X9221AYSI X9221AYSI Z X9221AWS X9221AWS Z X9221AWSI X9221AWSI Z X9221AUP X9221AUPZ X9221AUPI X9221AUPIZ X9221AUSI X9221AUSI Z 50 10 VCC LIMITS (V) 5 10% RTOTAL (k) 2 TEMP RANGE (C) 0 to +70 0 to +70 -40 to +85 -40 to +85 0 to +70 0 to +70 -40 to +85 -40 to +85 0 to +70 0 to +70 -40 to +85 -40 to +85 -40 to +85 -40 to +85 PACKAGE 20 Ld SOIC (300MIL) 20 Ld SOIC (300MIL) (Pb-Free) 20 Ld SOIC (300MIL) 20 Ld SOIC (300MIL) (Pb-Free) 20 Ld SOIC (300MIL) 20 Ld SOIC (300MIL) (Pb-Free) 20 Ld SOIC (300MIL) 20 Ld SOIC (300MIL) (Pb-Free) 20 Ld PDIP 20 Ld PDIP (Pb-Free) 20 Ld PDIP 20 Ld PDIP (Pb-Free) 20 Ld SOIC (300MIL) 20 Ld SOIC (300MIL) (Pb-Free) PKG. DWG. # MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0031 MDP0031 MDP0031 MDP0031 MDP0027 MDP0027
*Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
PIN DESCRIPTIONS Host Interface Pins Serial Clock (SCL) The SCL input is used to clock data into and out of the X9221A. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. Address The Address inputs are used to set the least significant 4 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9221A
Potentiometer Pins VH/RH(VH0/RH0-VH1/RH1), VL/RL (VL0/RL0-VL1/RL1) The VH/RH and VL/RL inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. VW/RW (VW0/RW0-VW1/RW1) The wiper outputs are equivalent to the wiper output of a mechanical potentiometer. PIN CONFIGURATION
DIP/SOIC VW0/RW0 VL0/RL0 VH0/RL0 A0 A2 VW1/RW1 VL1/RL1 VH1/RH1 SDA VSS 1 2 3 4 5 6 7 8 9 10 X9221A 20 19 18 17 16 15 14 13 12 11 VCC RES RES RES A1 A3 SCL RES RES RES
2
FN8163.2 August 30, 2006
X9221A
PIN NAMES Symbol
SCL SDA A0-A3 VH0/RH0-VH1/RH1, VL0/RH0-VL1/RL0 VW0/RW0-VW1/RW1 RES
Acknowledge Description
Serial Clock Serial Data Address Potentiometers (terminal equivalent) Potentiometers (wiper equivalent) Reserved (Do not connect)
Acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. The transmitting device, either the master or the slave, will release the SDA bus after transmitting eight bits. The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to acknowledge that it successfully received the eight bits of data. See Figure 7. The X9221A will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. If the command is followed by a data byte the X9221A will respond with a final acknowledge. Array Description The X9221A is comprised of two resistor arrays. Each array contains 63 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (VH/RH and VL/RL inputs). At both ends of each array and between each resistor segment is a FET switch connected to the wiper (VW/RW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by the Wiper Counter Register (WCR). The six least significant bits of the WCR are decoded to select, and enable, one of sixty-four switches. The WCR may be written directly, or it can be changed by transferring the contents of one of four associated data registers into the WCR. These data registers and the WCR can be read and written by the host system. Device Addressing Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (refer to Figure 1 below). For the X9221A this is fixed as 0101[B]. Figure 1. Slave Address
Device Type Identifier 0 1 0 1 A3 A2 A1 A0
PRINCIPLES OF OPERATION The X9221A is a highly integrated microcircuit incorporating two resistor arrays, their associated registers and counters and the serial interface logic providing direct communication between the host and the XDCP potentiometers. Serial Interface The X9221A supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X9221A will be considered a slave device in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW periods (tLOW). SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Start Condition All commands to the X9221A are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH (tHIGH). The X9221A continuously monitors the SDA and SCL lines for the start condition, and will not respond to any command until this condition is met. Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA while SCL is HIGH.
Device Address
3
FN8163.2 August 30, 2006
X9221A
The next four bits of the slave address are the device address. The physical device address is defined by the state of the A0-A3 inputs. The X9221A compares the serial data stream with the address input state; a successful compare of all four address bits is required for the X9221A to respond with an acknowledge. Acknowledge Polling The disabling of the inputs, during the internal nonvolatile write operation, can be used to take advantage of the typical 5ms EEPROM write cycle time. Once the stop condition is issued to indicate the end of the nonvolatile write command the X9221A initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the device slave address. If the X9221A is still busy with the write operation no ACK will be returned. If the X9221A has completed the write operation an ACK will be returned and the master can then proceed with the next operation. Flow 1. ACK Polling Sequence
Nonvolatile Write Command Completed Enter ACK Polling
Instruction Structure The next byte sent to the X9221A contains the instruction and register pointer information. The four most significant bits are the instruction. The next four bits point to one of two pots and when applicable they point to one of four associated registers. The format is shown below in Figure 2. Figure 2. Instruction Byte Format
t
Potentiometer Select I3 I2 I1 I0 0 P0 R1 R0
Instructions
Register Select
The four high order bits define the instruction. The sixth bit (P0) selects which one of the two potentiometers is to be affected by the instruction. The last two bits (R1 and R0) select one of the four registers that is to be acted upon when a register oriented instruction is issued. Four of the nine instructions end with the transmission of the instruction byte. The basic sequence is illustrated in Figure 3. These two-byte instructions exchange data between the WCR and one of the data registers. A transfer from a data register to a WCR is essentially a write to a static RAM. The response of the wiper to this action will be delayed tSTPWV. A transfer from WCR's current wiper position to a data register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between either potentiometer and their associated registers or it may occur between both of the potentiometers and one of their associated registers. Four instructions require a three-byte sequence to complete. These instructions transfer data between the host and the X9221A; either between the host and one of the data registers or directly between the host and the WCR. These instructions are: Read WCR, read the current wiper position of the selected pot; Write WCR, change current wiper position of the selected pot; Read Data Register, read the contents of the selected nonvolatile register; Write Data Register, write a new value to the selected data register. The sequence of operations is shown in Figure 4. The Increment/Decrement command is different from the other commands. Once the command is issued and the X9221A has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine
Issue START
Issue Slave Address
Issue STOP
ACK Returned? YES
NO
Further Operation? YES Issue Instruction
NO
Issue STOP
Proceed
Proceed
4
FN8163.2 August 30, 2006
X9221A
tuning capability to the host. For each SCL clock pulse (tHIGH) while SDA is HIGH, the selected wiper will move one resistor segment towards the VH/RH terminal. Similarly, for each SCL clock pulse while SDA is Figure 3. Two-Byte Command Sequence LOW, the selected wiper will move one resistor segment towards the VL/RL terminal. A detailed illustration of the sequence and timing for this operation are shown in Figures 5 and 6 respectively.
SCL
SDA S T A R T 0 1 0 1 A3 A2 A1 A0 A C K I3 I2 I1 I0 0 P0 R1 R0 A C K S T O P
Figure 4. Three-Byte Command Sequence
SCL
SDA S T A R T 0 1 0 1 A3 A2 A1 A0 A C K I3 I2 I1 I0 0 P0 R1 R0 A C K 0 0 D5 D4 D3 D2 D1 D0 A C K S T O P
Figure 5. Increment/Decrement Command Sequined
e
SCL
SDA S T A R
T
X
X
0
1
0
1
A3 A2 A1 A0
A C K
I3
I2
I1
I0
0
P0 R1 R0 A C K
I N C 1
I N C 2
I N C n
D E C 1
D E C n
S T O P
5
FN8163.2 August 30, 2006
X9221A
Figure 6. Increment/Decrement Timing Limits
INC/DEC CMD Issued SCL
tCLWV
SDA
VW/RW
Voltage Out
Table 1. Instruction Set Instruction Format Instruction
Read WCR Write WCR Read Data Register Write Data Register XFR Data Register to WCR XFR WCR to Data Register Global XFR Data Register to WCR Global XFR WCR to Data Register Increment/Decrement Wiper
Note:
I3
1 1 1 1 1 1 0
I2
0 0 0 1 1 1 0
I1
0 1 1 0 0 1 0
I0
1 0 1 0 1 0 1
0
0 0 0 0 0 0 N/A
P0
1/0 1/0 1/0 1/0 1/0 1/0 N/A
N/A(7) N/A 1/0 1/0 1/0 1/0 1/0
R1
R0
N/A N/A 1/0 1/0 1/0 1/0 1/0
Operation
Read the contents of the Wiper Counter Register pointed to by P0 Write new value to the Wiper Counter Register pointed to by P0 Read the contents of the Register pointed to by P0 and R1-R0 Write new value to the Register pointed to by P0 and R1-R0 Transfer the contents of the Register pointed to by P0 and R1-R0 to its associated WCR Transfer the contents of the WCR pointed to by P0 to the Register pointed to by R1-R0 Transfer the contents of the Data Registers pointed to by R1-R0 of both pots to their respective WCR Transfer the contents of all WCRs to their respective data Registers pointed to by R1-R0 of both pots Enable Increment/decrement of the WCR pointed to by P0
1
0
0
0
N/A
N/A
1/0
1/0
0
0
1
0
0
1/0
N/A
N/A
(7) N/A = Not applicable or don't care; that is, a data register is not involved in the operation and need not be addressed (typical)
6
FN8163.2 August 30, 2006
X9221A
Figure 7. Acknowledge Response from Receiver
SCL from Master
1
8
9
Data Output from Transmitter
Data Output from Receiver START Acknowledge
DETAILED OPERATION Both XDCP potentiometers share the serial interface and share a common architecture. Each potentiometer is comprised of a resistor array, a wiper counter register and four data registers. A detailed discussion of the register organization and array operation follows. Wiper Counter Register The X9221A contains two wiper counter registers (WCR), one for each XDCP potentiometer. The WCR can be envisioned as a 6-bit parallel and serial load counter with its outputs decoded to select one of sixtyfour switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the Write WCR instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers via the XFR Data Register instruction (parallel load); it can be modified one step at a time by the Increment/ Decrement instruction; finally, it is loaded with the contents of its data register zero (R0) upon power-up.
The WCR is a volatile register; that is, its contents are lost when the X9221A is powered-down. Although the register is automatically loaded with the value in R0 upon power-up, it should be noted this may be different from the value present at power-down. Data Registers Each potentiometer has four nonvolatile data registers. These can be read or written directly by the host and data can be transferred between any of the four data registers and the WCR. It should be noted all operations changing data in one of these registers is a nonvolatile operation and will take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, these registers can be used as regular memory locations that could possibly store system parameters or user preference data.
7
FN8163.2 August 30, 2006
X9221A
Figure 8. Detailed Potentiometer Block Diagram
Serial Data Path From Interface Circuitry Register 0 8 Register 1 6
Serial Bus Input
VH/RH
Parallel Bus Input Wiper Counter Register
Register 2
Register 3
C o u n t e r
If WCR = 00[H] then VW/RW = VL/RL If WCR = 3F[H] then VW/RW = VH/RH
UP/DN Modified SCL
INC/DEC Logic UP/DN CLK
D e c o d e VL/RL
VW/RW
8
FN8163.2 August 30, 2006
X9221A
ABSOLUTE MAXIMUM RATINGS Temperature Under Bias ................... -65C to +135C Storage Temperature ........................ -65C to +150C Voltage on SCK, SCL or Any Address Input With Respect to VSS ...................... -1V to +7V Voltage on Any VH/RH, VW/RW or VL/RL Referenced to VSS ................................. +6V / -4.3V V = |VH/RH-VL/RL|........................................... 10.3V Lead Temperature (soldering, 10s) ................. +300C IW (10s) ..............................................................6mA RECOMMENDED OPERATING CONDITIONS Temp Commercial Industrial Min. 0C -40C Max. +70C +85C Supply Voltage X9221A Limits 5V 10% COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those indicated in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Limits Symbol
RTOTAL IW RW VTERM
Parameter
End to End Resistance Power Rating Wiper Current Wiper Resistance Voltage on any VH/RH, VW/RW or VL/RL Pin Noise Resolution Absolute Linearity(1) Relative Linearity(2) Temperature Coefficient Radiometric Temperature Coefficient
Min.
-20 -3
Typ.
Max.
+20 50 +3
Unit
% mW mA V dBV %
Test Conditions
+25C, each pot Wiper Current = 1mA
40 -3.0 120 1.6 -1 -0.2 300
130 +5
Ref: 1V See Note 5 Vw(n)(actual - Vw(n)(expected) Vw(n + 1) - [Vw(n) + MI] See Note 5 See Note 5 See circuit #3
+1 +0.2 20 10/10/25
MI(3) MI(3) ppm/C ppm/C pF
CH/CL/CW Potentiometer Capacitances
9
FN8163.2 August 30, 2006
X9221A
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Limits Symbol
lCC ISB ILI ILO VIH VIL VOL
Parameter
Supply Current (Active) VCC Current (Standby) Input Leakage Current Output Leakage Current Input HIGH Voltage Input LOW Voltage Output LOW Voltage
Min. Typ.
200
Max.
3 500 10 10
Unit
mA A A A V V V IOL = 3mA
Test Conditions
fSCL = 100kHz, SDA = Open, Other Inputs = VSS SCL = SDA = VCC, Addr. = VSS VIN = VSS to VCC VOUT = VSS to VCC
2 -1
VCC + 1 0.8 0.4
Notes: (1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (3) MI = RTOT/63 or (VH/RH-VL/RL)/63, single pot
ENDURANCE AND DATA RETENTION Parameter
Minimum endurance Data retention
Min.
100,000 100
Unit
Data changes per bit per register years
CAPACITANCE Symbol
CI/O CIN
(5) (5)
Parameter
Input/output capacitance (SDA) Input capacitance (A0, A1, A2, A3 and SCL)
Max.
8 6
Unit
pF pF
Test Conditions
VI/O = 0V VIN = 0V
POWER-UP TIMING Symbol
tPUW(6) tRVCC tPUR
(6)
Parameter
Power-up to initiation of read operation Power-up to initiation of write operation VCC Power-up ramp rate
Min.
Max.
1 5
Unit
ms ms V/ms
0.2
50
Notes: (5) This parameter is periodically sampled and not 100% tested. (6) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested.
Power Up Requirements (Power up sequencing can affect correct recall of the wiper registers) The preferred power-on sequence is as follows: First VCC, then the potentiometer pins. It is suggested that VCC reach 90% of its final value before power is applied to the potentiometer pins. The VCC ramp rate specification should be met, and any glitches or slope changes in the VCC line should be held to <100mV if possible. Also, VCC should not reverse polarity by more than 0.5V.
10
FN8163.2 August 30, 2006
X9221A
A.C. CONDITIONS OF TEST
Input pulse levels Input rise and fall times Input and output timing levels VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5
SYMBOL TABLE Circuit #3 SPICE Macro Model
WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don't Care: Changes Allowed N/A OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance RH Macro Model RTOTAL CH 10pF CW 25pF RW CL 10pF RL
Guidelines for Calculating Typical Values of Bus Pull-Up Resistors
120 V RMIN = CC MAX =1.8k IOL MIN t RMAX = R CBUS Max. Resistance
Equivalent A.C. Test Circuit
5V Resistance (k) 1533 SDA Output 100pF
100 80 60 40 20 0 0
Min. Resistance 20 40 60 80 100 120
Bus Capacitance (pF)
11
FN8163.2 August 30, 2006
X9221A
A.C. CHARACTERISTICS (Over recommended operating conditions unless otherwise stated) Limits Symbol
fSCL tLOW tHIGH tR tF Ti tSU:STA tHD:STA tSU:DAT tHD:DAT tAA tDH tSU:STO tBUF tWR tSTPWV tCLWV SCL clock frequency Clock LOW period Clock HIGH period SCL and SDA rise time SCL and SDA fall time Noise suppression time constant (glitch filter) Start condition setup time (for a repeated start condition) Start condition hold time Data in setup time Data in hold time SCL LOW to SDA data out valid Data out hold time Stop condition setup time Bus free time prior to new transmission Write cycle time (nonvolatile write operation) Wiper response time from stop generation Wiper response from SCL LOW 4700 4000 250 0 300 300 4700 4700 10 1000 500 3500
Parameter
Min.
0 4700 4000
Max.
100
Unit
kHz ns ns
Reference Figure
10 10 10 10 10 10 10 & 12 10 & 12 10 10 11 11 10 & 12 10 13 13 6
1000 300 100
ns ns ns ns ns ns ns ns ns ns ns ms s s
TIMING DIAGRAMS Figure 10. Input Bus Timing
tLOW tR
tHIGH SCL tSU:STA SDA (Data in) tHD:STA tHD:DAT
tF
tSU:DAT
tSU:STO
tBUF
Figure 11. Output Bus Timing
SCL tAA SDA SDAOUT (ACK) tDH SDAOUT SDAOUT
12
FN8163.2 August 30, 2006
X9221A
Figure 12. Start Stop Timing
START Condition SCL tSU:STA SDA (Data in) tHD:STA
STOP Condition
tSU:STO
Figure 13. Write Cycle and Wiper Response Timing
SCL
Clock 8
Clock 9
STOP tWR
START
SDA
SDAIN
ACK tSTPWV
Wiper Output
13
FN8163.2 August 30, 2006
X9221A Small Outline Package Family (SO)
A D N (N/2)+1 h X 45
A E E1 PIN #1 I.D. MARK c SEE DETAIL "X"
1 B
(N/2) L1
0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X
SEATING PLANE L 4 4
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX 0.003 0.002 0.003 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. L 2/01
14
FN8163.2 August 30, 2006
X9221A Plastic Dual-In-Line Packages (PDIP)
D E N PIN #1 INDEX
SEATING PLANE L e b
A2
A c
E1
A1 NOTE 5
eA eB
1
2 b2
N/2
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE SYMBOL A A1 A2 b b2 c D E E1 e eA eB L N NOTES: 1. Plastic or metal protrusions of 0.010" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane. 4. Dimension eB is measured with the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. PDIP8 0.210 0.015 0.130 0.018 0.060 0.010 0.375 0.310 0.250 0.100 0.300 0.345 0.125 8 PDIP14 0.210 0.015 0.130 0.018 0.060 0.010 0.750 0.310 0.250 0.100 0.300 0.345 0.125 14 PDIP16 0.210 0.015 0.130 0.018 0.060 0.010 0.750 0.310 0.250 0.100 0.300 0.345 0.125 16 PDIP18 0.210 0.015 0.130 0.018 0.060 0.010 0.890 0.310 0.250 0.100 0.300 0.345 0.125 18 PDIP20 0.210 0.015 0.130 0.018 0.060 0.010 1.020 0.310 0.250 0.100 0.300 0.345 0.125 20 TOLERANCE MAX MIN 0.005 0.002 +0.010/-0.015 +0.004/-0.002 0.010 +0.015/-0.010 0.005 Basic Basic 0.025 0.010 Reference Rev. B 2/99 2 1 NOTES
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 15
FN8163.2 August 30, 2006

▲Up To Search▲

Price & Availability of X9221A06

	To Download X9221A06 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .